BCON for LVDS Interface Description#

This topic describes Basler's proprietary BCON for LVDS interface.

The Basler BCON for LVDS interface offers the highest flexibility for connecting with LVDS -based technology like FPGA boards and SoCs (Systems on a Chip).

Interface Specifications#

Specification Value Notes
Data lanes 4
Clock lines 1 Used for the word clock.
Control lines 3 I²C interface lines (clock, data, ID).
Input lines 1
Output lines 1
Serialization factor 7
Data bus width 28 bit
Bus width reserved for image data 24 bit
Word clock frequency 12–84 MHz Settable in increments of 8.
Word clock duty cycle 4/7
Bit clock frequency fWordClk * 7

The BCON for LVDS specifications are similar to the ChannelLink-I specifications, in particular the specifications for Texas Instrument's DS90CR28x deserializer. This applies to the following:

  • Separation of data, clock, and control lines
  • Number of data lanes
  • Serialization factor
  • Bus width
  • Clock frequencies
  • Word clock duty cycle

For more information about Channel Link, see the Channel Link Design Guide.

Info

Because the Camera Link interface is also based on Channel Link, it can be compared to the BCON for LVDS interface. For more information, see the Comparison of Basler BCON for LVDS and Camera Link Interfaces application note.

Data Output#

The data output by the four data lanes (X0, X1, X2, X3) consists of the following information:

  • Frame valid bit (FVal): Indicates that a valid frame is being transmitted.
  • Line valid bit (LVal): Indicates that a valid line is being transmitted.
  • Frame information (FrameInfo): Includes information about the pixel format and the number of pixels per clock cycle. Sent before each frame transmission.
  • Pixel data (Line 1, Line 2, …, Line n): Pixel data, line by line.
  • Line checksum (Cksum 1, Cksum 2, …, Cksum n): Check sum for each line of pixel data. Sent after each line transmission.
  • Output bits (Output 0 and Output 1): Two bits that can be used to transmit output signals, e.g. Flash Window or Exposure Active.

Frame information, pixel data, and line checksums are transmitted on a common 24-bit image data channel ("Data").

Data Flow#

The BCON for LVDS interface does not provide data flow control. Also, unlike the CameraLink interface, the interface does not provide a data valid bit (DVal). Only FVal and LVal are used as synchronization signals:

BCON for LVDS Data Flow Diagram

Whenever FVal is low and the camera module is not sending FrameInfo or Cksum data, a sync pattern is transmitted. This allows you to set up the correct word alignment.

Data Serialization and Timing#

BCON for LVDS Serialization and Timing

As shown above, data output is serialized using up to 28 bits on up to four data lanes (X0 to X3).

  • Two bits are reserved for the output signals (Output 0 and Output 1). They are always transmitted on data lane X0 at position 0 and 1.
  • Another two bits are reserved for the synchronization signals (FVal and LVal). They are always transmitted on data lane X0 at position 2 and 3.
  • The remaining 24 bits are reserved for the image data channel including frame information, pixel data, and line checksums.

The actual number of bits and active data lanes used depends on the data being transmitted:

Data Transmitted Bits Used Data Lanes Active
Frame information
8-bit pixel data
8-bit checksum
Bit 0 – Bit 7 X0, X1
12-bit pixel data
12-bit checksum
Bit 0 – Bit 11 X0, X1, X2
16-bit pixel data
16-bit checksum
Bit 0 – Bit 15 X0, X1, X2
24-bit pixel data
24-bit checksum
Bit 0 – Bit 23 X0, X1, X2, X3

Info

If you are only using 8-bit pixel formats, e.g. because you are using a monochrome camera module, the X2 and X3 data lanes are never active. Accordingly, if you are only using 8-bit or 12-bit pixel formats, X3 is never active.

Basler recommends, however, to always connect all LVDS data lanes from X0 to X3.

Frame Valid Bit and Line Valid Bit#

The frame valid bit (FVal) and the line valid bit (LVal) indicate that a valid frame or line is being transmitted.

LVal and FVal are transmitted on data lane X0 at position 2 and 3.

Frame Information#

As shown on the data flow diagram, a "FrameInfo" block is sent before each frame transmission.

Each FrameInfo block includes the following information:

  • Pixel format valid for the following pixel data.
  • Number of pixels per clock cycle.

Frame information is always transmitted on bits 0 through 7 of the 24-bit data channel:

Data Channel Usage During FrameInfo Transmission

In every FrameInfo block, the camera module transmits the following information:

Clock Cycle Description Bit Length Enumeration     Value
n Command Word 8 - 0b10111101
n+1 Pixels per clock cycle value 8 One
Two
0b00000000
0b00000001
n+2

n+5
Pixel format value
Transmitted in 4 Bytes, least significant byte sent first
Adheres to the GenICam Pixel Format Names and Values specification.
32 Mono 8
Mono 12
Bayer GR 8a
Bayer RG 8a
Bayer GB 8a
Bayer BG 8a
Bayer GR 12a
Bayer RG 12a
Bayer GB 12a
Bayer BG 12a
YCbCr422
RGB 8
0x01080001
0x01100005
0x01080008
0x01080009
0x0108000A
0x0108000B
0x01100010
0x01100011
0x01100012
0x01100013
0x0210003B
0x02180014

  1. The standard Bayer filter alignment for Basler dart BCON for LVDS camera modules is GB. If supported, other alignments can be set using the Reverse X and Reverse Y feature.

  2. Sample image data per clock cycle.

Example#

If the camera module is configured for two pixels per clock cycle and Mono 12 pixel data, the camera module sends the following information before each frame transmission:

Clock Cycle Data Notes
n 0b10111101 Command Word
n+1 0b00000001 Two pixels per clock cycle
n+2 0b00000101 Mono 12 pixel format value
n+3 0b00000000 Mono 12 pixel format value
n+4 0b00010000 Mono 12 pixel format value
n+5 0b00000001 Mono 12 pixel format value

Mono 12 pixel format value = 0x01100005 = 0b00000001 00010000 00000000 00000101 (least significant byte sent first)

Line Checksum#

To detect transmission errors, the Basler BCON for LVDS interface uses even parity.

For each image line, a checksum is calculated. The checksum is added to the output data at the end of each line. The checksum consists of a number of parity bits depending on the selected pixel format. For every bit position of every pixel of the current line, an even parity bit is calculated.

The checksum is transmitted directly after the data of the last pixel in the image line has been transmitted (see data flow diagram).

Example: Assume the camera module is set to Mono 8 pixel data and one pixel per clock cycle. Also assume that the image ROI width is set to 5 pixels only. This means that each image line consists of 5 x 8 bit image data. The table below shows sample data for one image line under these conditions.

Data Channel Bit Position nb n+1 n+2 n+3 n+4 Count of 1-bits Checksum Bit (Even Parity Bit)  
Bit 0 1 1 0 1 0 3 1 LSB
Bit 1 1 0 1 0 0 2 0  
Bit 2 1 0 0 0 0 1 1  
Bit 3 1 1 1 0 1 4 0  
Bit 4 1 0 1 0 0 2 0  
Bit 5 0 0 0 1 1 2 0  
Bit 6 0 0 0 0 0 0 0  
Bit 7 1 1 0 0 1 3 1 MSB

In the example shown above, the line checksum data is 0b10000101.

Sync Pattern#

Whenever the frame valid bit (FVal) is low and the camera module is not sending frame information or line checksum data, a fixed sync pattern is transmitted. This allows you to set up the correct word alignment.

BCON for LVDS Sync Pattern

Output Bits#

The BCON for LVDS interface provides two bits that can be used to transmit two output signals: Output 0 and Output 1.

Output 0 and Output 1 are transmitted on data lane X0 at position 0 and 1.

Depending on the camera model, the following output signals are available:

  • Flash Window
  • Exposure Active
  • User Output 1
  • User Output 2

For more information about configuring output signals, see the Line Source feature.

Pixel Data#

Pixel Formats#

Pixel Format Available on Bit Depth
Mono 8 Mono camera modules only 8
Bayer 8 Color camera modules only 8
Mono 12 Mono camera modules only 12
Bayer 12 Color camera modules only 12
YCbCr422 Color camera modules only 16
RGB 8 Color camera modules only 24

For image data transmission, the BCON for LVDS interface does not distinguish between the individual 8-bit pixel formats (Mono 8 / Bayer 8). Similarly, the interface does not distinguish between the individual 12-bit pixel formats (Mono 12 / Bayer 12).

However, information about the specific pixel format used for frame acquisition is included in the FrameInfo part of the data stream.

Pixels per Clock Cycle#

On all Basler BCON for LVDS camera modules, you can set the number of pixels transmitted per clock cycle.

One Pixel per Clock Cycle

This mode is available for all available pixel formats.

In this mode, the camera module transmits pixel data as follows:

  • On each clock cycle, data for one pixel is transmitted via the BCON for LVDS interface.
  • On the first clock cycle, the camera module transmits the data for the first pixel in line one. On the second clock cycle, the camera module transmits the data for the second pixel in line one, and so on until the line is complete.
  • When line one is complete, the camera module sends a checksum for the line. After that, transmission of line two begins and proceeds in a similar fashion. Data transmission continues line by line until all frame data has been transmitted.

During pixel data transmission, the 24 bits of the data channel will be used as shown below:

Data Channel Usage (One Pixel per Clock Cycle)

Two Pixels per Clock Cycle

This mode is only available for 8-bit and 12-bit pixel formats (i.e., not available for YCbCr422 and RGB 8 pixel formats).

In this mode, the camera module transmits pixel data as follows:

  • On each clock cycle, the data for two pixels are transmitted via the BCON for LVDS interface.
  • On the first clock cycle, the camera module transmits the data for the first two pixels in line one. On the second clock cycle, the camera module transmits the data for the next two pixels in line one, and so on until the line is complete.
  • When line one is complete, the camera module sends a checksum for the line. After that, transmission of line two begins and proceeds in a similar fashion. Data transmission continues line by line until all frame data has been transmitted.

During pixel data transmission, the 24 bits of the data channel will be used as shown below:

Data Channel Usage (Two Pixels per Clock Cycle)

Setting the Number of Pixels per Clock Cycle

To set the number of pixels per clock cycle, set the BconPixelsPerClockCycle parameter to One or Two.

You can find sample code below.

Info

The pylon API also provides a PixelPerClockCycle parameter that sets the pixels per clock cycle on host side. The parameter should be set to the same value as the BconPixelsPerClockCycle parameter. When you change the BconPixelsPerClockCycle parameter, the PixelPerClockCycle automatically adapts, but not vice versa.

Output Clock#

The base clock for the BCON for LVDS output is the word clock WordClk. Its frequency can range from 12 MHz to 84 MHz (settable in increments of 8, i.e. 12, 20, 28, etc.).

The word clock duty cycle is 4/7, i.e, the word clock signal is active (high) during 4/7 of each period (≈57.14 % of the time).

The word clock is transmitted on the separate output clock line XCLK.

The bit clock frequency fBitClk is not transmitted, but can be calculated. The bit clock frequency is 7 times faster than the word clock frequency:

fBitClk = fWordClk * 7

Setting the Clock Speed#

To set the clock speed, set the BconClockFrequency parameter to one of the following values:

  • MHz_12
  • MHz_20
  • MHz_28
  • MHz_36
  • MHz_44
  • MHz_52
  • MHz_60
  • MHz_68
  • MHz_76
  • MHz_84

You can find sample code below.

Info

The pylon API also provides a ClockFrequency parameter that sets the pixels per clock cycle on stream grabber side. The ClockFrequency and BconClockFrequency parameters are automatically synchronized. When you change one parameter, the other one adapts, and vice versa.

Input Line#

The BCON for LVDS input line can be used to send a trigger or other input signals to the camera module.

The state of the input can be read via the camera module's control interface at any time.

In the pylon API, the input line is Line 3.

I²C Interface#

The camera module is configured via a standard I²C interface. For a detailed description, refer to the I²C-bus Specification and User Manual.

I²C Features#

In addition to the mandatory I²C features, BCON for LVDS uses the optional Clock Stretching feature, i.e., it may hold I2C_SCL low.

Info

When designing your system, make sure that the I²C master can handle clock stretching.

For detailed information about the features, see the I²C-bus Specification and User Manual.

Basler-Specific Settings#

The following sections provide information about settings that deviate from the I²C bus specifications.

General Information#

The control channel of the BCON for LVDS interface is designed as an I²C bus interface. A BCON for LVDS camera module is an I²C slave device that can handle data transfers at up to 400 kbit/s ("Fast Mode" according to I²C).

Fast Mode (Fm) devices are downward compatible and can communicate with Standard Mode (Sm) devices in a 0 to 100 kbit/s I²C bus system.

However, as they are not upward compatible, Fast Mode devices should not be integrated in an I²C bus system that is configured for a faster mode, i.e. Fast Mode Plus (Fm+) or High Speed Mode (Hs). Fast Mode devices cannot follow the higher transfer rate of the faster modes. Therefore, unpredictable states might occur.

These limitations have to be observed when designing the I²C bus master.

Additional I²C Control Line (I2C_ID)#

In addition to the standard I²C control lines (I2C_SDA data line, I2C_SCL clock line), there is an additional I²C control line, the I2C_ID line.

Normally, the I2C_ID line lets you define the slave address that the camera module should respond to. You can connect up to two camera modules to a single I²C bus. The logical level of the I2C_ID line determines which slave address is used (i.e., to which the camera module should respond).

Logical Level of I2C_ID Line Slave Address Communication with
0 (low) 0x3c Camera module 1
1 (high) 0x3d Camera module 2

Normally, the I2C_ID line is permanently wired to a fixed level, either low (0 V) or high (3.3 V), depending on the desired slave address.

The I2C_ID line can also be used to reset the camera module. For more information, see below.

Reset via I2C_ID Line#

If the camera module does not respond anymore, you can activate a reset function via the I2C_ID line.

Info

When you switch on the supply voltage, ensure the following:

  • The I2C_ID line must have the correct logical level according to the desired slave address.
  • The logical level at system start must not be changed during operation, only in case of a reset.

To reset the camera module:

  1. Set the I2C_ID line to the opposite logical level for at least 100 ms.
  2. Set the I2C_ID line back to its original logical level. The switch back will trigger the reset of the microcontroller. The FPGA will be reloaded, but not reset.

Sample Code#

// Configure the camera to transmit two pixels per clock cycle
camera.BconPixelsPerClockCycle.SetValue(BconPixelsPerClockCycle_Two);
// Set the BCON output clock speed to 84 MHz
camera.BconClockFrequency.SetValue(BconClockFrequency_MHz_84);
INodeMap& nodemap = camera.GetNodeMap();
// Configure the camera to transmit two pixels per clock cycle
CEnumerationPtr(nodemap.GetNode("BconPixelsPerClockCycle"))->FromString("Two");
// Set the BCON output clock speed to 84 MHz
CEnumerationPtr(nodemap.GetNode("BconClockFrequency"))->FromString("MHz");
INodeMap& nodemap = camera.GetNodeMap();
// Configure the camera to transmit two pixels per clock cycle
CEnumParameter(nodemap, "BconPixelsPerClockCycle").SetValue("Two");
// Set the BCON output clock speed to 84 MHz
CEnumParameter(nodemap, "BconClockFrequency").SetValue("MHz");
// Configure the camera to transmit two pixels per clock cycle
camera.Parameters[PLCamera.BconPixelsPerClockCycle].SetValue(PLCamera.BconPixelsPerClockCycle.Two);
// Set the BCON output clock speed to 84 MHz
camera.Parameters[PLCamera.BconClockFrequency].SetValue(PLCamera.BconClockFrequency.MHz);
// Configure the camera to transmit two pixels per clock cycle
Pylon.DeviceFeatureFromString(hdev, "BconPixelsPerClockCycle", "Two");
// Set the BCON output clock speed to 84 MHz
Pylon.DeviceFeatureFromString(hdev, "BconClockFrequency", "MHz");
/* Macro to check for errors */
#define CHECK(errc) if (GENAPI_E_OK != errc) printErrorAndExit(errc)
GENAPIC_RESULT errRes = GENAPI_E_OK;  /* Return value of pylon methods */
/* Configure the camera to transmit two pixels per clock cycle */
errRes = PylonDeviceFeatureFromString(hdev, "BconPixelsPerClockCycle", "Two");
CHECK(errRes);
/* Set the BCON output clock speed to 84 MHz */
errRes = PylonDeviceFeatureFromString(hdev, "BconClockFrequency", "MHz");
CHECK(errRes);