Embedding and Simulating the IP core

You are ready now to integrate the IP core into your surrounding FPGA design. This basically means implementing and connecting converters between the data communication protocols of the target hardware and the protocols at the IP core interfaces. In particular, you need to care for connecting external interfaces like memory controller, sensor interface and data output.

When you generated the IP core black box (as described in section Generating VHDL Code for the IP Core), not only the IP core black box itself was generated. In the same step, a whole test bench was generated that is already tailored to test the individual interfaces of the IP core while you integrate them into your HDL design.

The test bench enables simulation of data communication through the IP core interfaces during HDL integration. The tools generated for HDL simulation focus on testing the interface protocols and generating stimuli for the circuits attached to the core in the top-level architecture (your HDL design).

In the test bench, each individual interface port which may later be connected via a corresponding VisualApplets operator is simulated independently, driven by file I/O. The simulation entity consists of the following elements:

  • Emulation of slave interface for register access: Configured by file, the simulation module provides a set of registers which can be written and read.
    There are dedicated registers which connect to the enable and reset signals. You can configure different processes1. Enable and Reset are the only signals which connect to the other simulation modules whose affiliation to a process you can specify through simulation entity parameters (see below).
    The register interface emulator provides the option to change register values over time according to a stimuli file.2
  • Emulator of image source connected to ImgOut ports. Stimulated by file, this kind of module outputs image data to the ImgOut interface of the IP core. The image protocol ID you can configure according to the image protocols you specified for an image output port.
  • Emulator of frame sink connected to ImgIn ports. This kind of module emulates an operator which is connected to the ImgIn interface of the IP core. The image protocol ID you can configure according to the image protocols you specified for an image input port. The module writes the received data to file.
  • Memory port emulator which acts as if a module is connected which uses RAM. The sequence of write and read accesses is stimulated by a file and read data is output to file.
  • GPIO emulator. Each GPIO signal for output is driven by a signal generator which is configured by a file. Each GPIO signal input is monitored and changes of the signal are written to a report file.

Figure 18: Example test bench for IP core with 1 ImgIn interface, 1 ImgOut interface, 1 memory interface, 1 GPI, 1 GPO, and slave interface