Table of Contents
- User Manual
- Tutorial and Examples
-
- Introduction
- Basic Design Theory
- Basic Acquisition Designs for Varying Camera Types and Hardware Platforms
-
- Basic Acquisition Examples for Camera Link Cameras for microEnable IV VD4-CL/-PoCL Frame Grabber
- Basic Acquisition Examples for GigE Vision Cameras for microEnable IV Frame Grabber
- Basic Acquisition Examples for Camera Link Cameras for marathon, LightBridge and ironman Frame Grabbers
- Basic Acquisition Examples for CoaXPress Cameras for marathon and ironman Frame Grabbers
- Processing Examples
- Parameter Library Examples
- Embedded VisualApplets
- Operator Reference
-
- Introduction
- Library Overview
- Library Accumulator
- Library Arithmetics
- Library Base
-
- BRANCH
- CastBitWidth
- CastColorSpace
- CastParallel
- CastType
- CONST
- ConvertPixelFormat
- Coordinate_X
- Coordinate_Y
- Dummy
- DynamicROI
- EventToHost
- ExpandToKernel
- GetStatus
- HierarchicalBox
- ImageNumber
- KernelRemap
- MergeComponents
- MergeKernel
- MergeParallel
- MergePixel
- NOP
- PARALLELdn
- PARALLELup
- PseudoRandomNumberGen
- SampleDn
- SampleUp
- SelectBitField
- SelectComponent
- SelectFromParallel
- SelectROI
- SelectSubKernel
- SetDimension
- SplitComponents
- SplitKernel
- SplitParallel
- Trash
- Library Blob
- Library Color
- Library Compression
- Library Debugging
- Library Filter
- Library Logic
- Library Memory
- Library Parameters
- Library Hardware Platform
-
- AppletProperties
- BoardStatus
- ActionCommand
- CameraControl
- BaseGrayCamera
- BaseRgbCamera
- MediumGrayCamera
- MediumRgbCamera
- FullGrayCamera
- FullRgbCamera
- CameraGrayArea
- CameraGrayAreaBase
- CameraGrayAreaFull
- CameraGrayAreaMedium
- CameraGrayLine
- CameraGrayLineBase
- CameraGrayLineFull
- CameraGrayLineMedium
- CameraRgbArea
- CameraRgbAreaBase
- CameraRgbAreaMedium
- CameraRgbLine
- CameraRgbLineBase
- CameraRgbLineMedium
- CLHSDualCamera
- CLHSPulseIn
- CLHSPulseOut
- CLHSSingleCamera
- CXPDualCamera
- CXPQuadCamera
- CXPSingleCamera
- DigIOPort
- DmaFromPC
- DmaToPC
- GPI
- GPO
- LED
- NativeTrgPortIn
- NativeTrgPortInExt
- NativeTrgPortOut
- RxLink
- TrgPortArea
- TrgPortLine
- TriggerIn
- TriggerOut
- TxLink
- SignalToEvent
- Library Prototype
- Library Signal
-
- DelayToSignal
- Downscale
- EventToSignal
- FrameEndToSignal
- FrameStartToSignal
- Generate
- GetSignalStatus
- Gnd
- LimitSignalWidth
- LineEndToSignal
- LineStartToSignal
- PeriodToSignal
- PixelToSignal
- Polarity
- PulseCounter
- RsFlipFlop
- RxSignalLink
- Select
- SetSignalStatus
- ShaftEncoder
- ShaftEncoderCompensate
- SignalDebounce
- SignalDelay
- SignalEdge
- SignalGate
- SignalToDelay
- SignalToPeriod
- SignalToPixel
- SignalToWidth
- SignalWidth
- SyncSignal
- TxSignalLink
- Vcc
- WidthToSignal
- Library Synchronization
- Library Transformation
- Appendix. Device Resources
- Glossary
- Bibliography
- Index
List of Figures
- 1. VisualApplets - From Idea to Image Processor in 15 Minutes
- 2. VisualApplets – Awarded Software Environment
- 3. Recommended Xilinx tools
- 4. VisualApplets Main Window
- 5. Start of a New Project
- 6. Dragging Operators from Libraries into the Design Window
- 7. Module Properties
- 8. Successful DRC
- 9. Build Settings for microEnable 5 / newer Xilinx ISE versions
- 10. Simple VisualApplets Design
- 11. The Design Workflow
- 12. Main Program Window
- 13. Operator not available for currently selected targed hardware platform
- 14. Project Info
- 15. Module Search
- 16. Module Search
- 17. DRC Log Information
- 18. Build Log Information
- 19. Example: Displaying Information on the CONST Operator
- 20. Library Panel with Operator Library on Display
- 21. Libary Panel with Operator Library on Display
- 22. Configuring the number of displayed recent designs
- 23. Start of a new Project
- 24. Edit Project Details
- 25. Menu Design, menu item Change FPGA Clock
- 26. Slider and spin box for selecting FPGA clock frequency
- 27. Operator Libraries
- 28. Error message in case an operator is not applicable for another hardware platform
- 29. Simple VisualApplets Design
- 30. Pixel Order
- 31. Model of a 2D Image Protocol
- 32. Model of a 1D Image Protocol
- 33. Model of an 0D Image Protocol
- 34. O-Type Network
- 35. Failing O-Type Network
- 36. Display of not correctly synchronized data flow in VisualApplets 2.2 and higher
- 37. M-type and O-type Network
- 38. M-type Operator with One Synchronous Input Group
- 39. M-type Operator with Asynchronous Inputs
- 40. Synchronization of Independet Sources
- 41. Deadlock at SYNC, figure a
- 42. Deadlock at SYNC, figure b
- 43. Fixed Deadlock
- 44. Deadlock Avoided
- 45. Bandwidth Limitation
- 46. Bandwidth Limitation Compensated
- 47. Infinite Source Connection Error
- 48. Infinite Source Connection OK
- 49. Infinite source conversion module (Buffer1) connected to a non-infinite source
- 50. O-type module with signal link inputs, sourced by different M-type modules
- 51. Module Properties Window
- 52. Field Parameter Edit Window
- 53. Function Dialog to Edit Field Parameters
- 54. Disabled Parameters
- 55. Parameters in Illegal States
- 56. Parameter in Warning State
- 57. Metadata Parameter
- 58. Invalid Source Port Link Properties
- 59. Invalid Destination Port Link Properties
- 60. Device Resource Allocation Window
- 61. Grayed-out resource CameraControl
- 62. Device Resource Conflict
- 63. Auto Correction of Device Resource Conflicts
- 64. DRC Level 1 Error
- 65. Analysis Menu
- 66.
- 67. Source Viewer Window
- 68. Viewing Options
- 69. Pixel Values
- 70. Zooming in the Magnifier
- 71. Thumbnail Display in Source
- 72. Highligted Image Section Used for Simulation
- 73. Crosshair Cursors in Display Window and Magnifier
- 74. Pixel Values
- 75. Image Dimensions
- 76. Exceeded Image Dimensions
- 77. Bit Widths of Image and Link
- 78. Defining Offset for Image Bits to Use
- 79. Display Properties for 4-bit Image
- 80. Defining Offset for Link Bits to Use
- 81. Display Alignment
- 82. Pixel Merge
- 83. Merging Factor = 1, Image Properties Do Not Fit Link Properties
- 84. Merging Factor = 2, Properties of Merged Image Fit Link Properties
- 85. Main Simulation Window
- 86. Changing Source and Probe Display
- 87. Non-connected Simulation Modules
- 88. Successful Simulation
- 89. Pixel Values Probe
- 90. Display of Undefined Image Areas
- 91. "Empty Image" Symbol
- 92. Link View
- 93. Save Options Dialog
- 94. File Format Options for Saving
- 95. Setting the Splitting Factor in the Save Options Dialog
- 96. Project Info Window
- 97. “View FPGA Resources” Button
- 98. Detailed Information on FPGA Resource Usage
- 99. Context Menu "Resources"
- 100. FPGA Resource Usage of Individual Module
- 101. Detected XILINX tools
- 102. Selecting the Build Configuration for Applet Build
- 103. Target Runtime Selection during Applet Build
- 104. Repacking Hardware Applet Files Window
- 105. Fullfilled Repacking Preconditions
- 106. Selecting Target Operating System
- 107. Display of Specified Repacking Settings
- 108. Message after Successful Repacking
- 109. SDK Generator
- 110. Example of a Hierarchical Box
- 111. Window tabs of the design window
- 112. Highlighting a port
- 113. Highlighting a port
- 114. Entering a port name
- 115. Renamed ports of a hierarchical box
- 116. Highlighting a port
- 117. Reordered input ports of a hierarchical box
- 118. User Libraries with Elements in the Library Panel
- 119. Saving a Hierarchical Box as a User Library Element
- 120. Adding documentation, version information, short description, and/or individual GUI Icon
- 121. Providing a password for a library element
- 122. Tooltip Information on User Library Element
- 123. Tooltip Information on User Library Element
- 124. Saving New User Library Element
- 125. Adding documentation, version information, short description, and/or individual GUI Icon
- 126. Providing a password for a library element
- 127. Tooltip Information on User Library Element
- 128.
- 129. Protecting a user library element
- 130. Entering password for protected user library element
- 131. Entering password for protected user library element
- 132. Replacement of Instances
- 133. Custom Library with operators deesigned with VisualApplets Expert
- 134. Applet with Two Processes
- 135. Target Hardware Porting
- 136. Error message in case an operator is not applicable for new hardware platform
- 137. Dialog window for path settings
- 138. Dialog window for simulation settings
- 139. Example: If you always create applets for a Win64 system, you can set this operating system platform here as the default platform:
- 140. Example: Win64 will be suggested by the program when you create a new applet design:
- 141. Dialog window for diagram settings
- 142. Dialog window for global build settings
- 143. Dialog window for common settings
- 144. Target Runtime Project Setting
- 145. Project Details
- 146. Diagram Layout Settings
- 147. Recommended Xilinx Tools
- 148. Selection of Hardware Platform
- 149. Build Settings Window
- 150. Vivado supported by target hardware design
- 151. Vivado not supported by target hardware design
- 152. Parameter Set Example: Developing for microEnable 5 or LightBridge
- 153. Defaut: All build flow steps activated
- 154. Subsequent build steps deactivated
- 155. Keeping build files of the individual build steps
- 156. Keeping build files of the individual build steps
- 157. Command Mode Options
- 158. Command Mode "Use platform default value"
- 159. Command Mode "Append to platform default value"
- 160. Command Mode "Overwrite platform default value"
- 161. Handling Options
- 162. Script Collection in the VisualApplets program window
- 163.
- 164.
- 165. Properties of Operator CameraGrayAreaBase
- 166. Changed the Link Bit Width of the Camera Operator
- 167. Bit Width Cannot be Changed at Buffer Module Output Link
- 168. Illegal Condition after Link Property Change
- 169. DRC Error Messages Invalid Parameters
- 170. Red Parameters show Illegal Condition
- 171. ConvertPixelFormat Operator Added for 16Bit Output
- 172. ShiftLeft Operator Added for 16Bit Output
- 173. Block Diagram of Threshold Binarization Design with Monitoring
- 174. Use of the Binarization Applet in microDisplay
- 175. VisualApplets design to switch between two cameras
- 176. Deadlock Configurations using InsertImage
- 177. Line Duplication
- 178. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Base Configuration Mode
- 179. Basic Acquisition for RGB Camera Link Area Scan Cameras in Base Configuration Mode
- 180. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Medium Configuration Mode
- 181. Basic Acquisition for RGB Camera Link Area Scan Cameras in Medium Configuration Mode
- 182. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Full Configuration Mode
- 183. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Full Configuration 10 Bit Mode
- 184. Basic Acquisition for Grayscale Camera Link Line Scan Cameras in Base Configuration Mode
- 185. Basic Acquisition for RGB Camera Link Line Scan Cameras in Base Configuration Mode
- 186. Basic Acquisition for Grayscale Camera Link Line Scan Cameras in Medium Configuration Mode
- 187. Basic Acquisition for Grayscale 12 Bit Camera Link Line Scan Cameras in Medium Configuration Mode
- 188. Basic Acquisition for Grayscale Camera Link Line Scan Cameras in Full Configuration Mode
- 189. Basic Acquisition for Grayscale GigE Vision Area Scan Cameras
- 190. Basic Acquisition for RGB GigE Vision Area Scan Cameras
- 191. Basic Acquisition for Grayscale GigE Vision Line Scan Cameras
- 192. Basic Acquisition for RGB GigE Vision Line Scan Cameras
- 193. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Base Configuration Mode on LightBridge VCL, marathon VCL and ironman VCL
- 194. Basic Acquisition for RGB Camera Link Area Scan Cameras in Base Configuration Mode on LightBridge VCL, marathon VCL and ironman VCL
- 195. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Medium Configuration Mode on LightBridge VCL, marathon VCL and ironman VCL
- 196. Basic Acquisition for RGB Camera Link Area Scan Cameras in Base Configuration Mode on LightBridge VCL, marathon VCL and ironman VCL
- 197. Basic Acquisition Design for marathon VCL, LightBridge VCL and ironman VCL Frame Grabber for Camera Link Area Scan Cameras in Full Configuration Mode
- 198. Basic Acquisition Design for marathon, LightBridge and ironman Frame Grabber for Grayscale Camera Link Line Scan Cameras in Base Configuration Mode
- 199. Basic Acquisition for Grayscale Camera Link Line Scan Cameras in Base Configuration Mode on the LightBridge VCL, marathon VCL and ironman VCL
- 200. Basic Acquisition Design for marathon, LightBridge and ironman Frame Grabber for RGB Camera Link Line Scan Cameras in Base Configuration Mode
- 201. Basic Acquisition Design for marathon, LightBridge and ironman Frame Grabber for Grayscale Camera Link Line Scan Cameras in Base Configuration Mode
- 202. Basic Acquisition Design for marathon, LightBridge and ironman Frame Grabber for RGB Camera Link Line Scan Cameras in Base Configuration Mode
- 203. Basic Acquisition for marathon, LightBridge and ironman Frame Grabber for Camera Link Line Scan Cameras in Full Configuration Mode
- 204. Basic Acquisition for Grayscale CoaxPress Area Scan Cameras in 6GBit/s Mode with Link Aggregation 1 on the ironman Frame Grabber
- 205. Basic Acquisition for RGB CoaxPress Area Scan Cameras in 6 Gbit/s Mode with Link Aggregation 2 on the ironman Frame Grabber
- 206. Basic Acquisition for Grayscale CoaxPress Area Scan Cameras in 6 Gbit/s Mode with Link Aggregation 4 on the ironman Frame Grabber
- 207. Basic Acquisition for Grayscale CoaxPress Area Scan Cameras in 6 Gbit/s Mode with Link Aggregation 4 on the marathon Frame Grabber
- 208. Basic Acquisition for Grayscale CoaxPress Line Scan Cameras in 6 GBit/s Mode with Link Aggregation 1 on the ironman Frame Grabber
- 209. Basic Acquisition for RGB CoaxPress Line Scan Cameras in 6 Gbit/s Mode with Link Aggregation 2 on the ironman Frame Grabber
- 210. Basic Acquisition for Grayscale CoaxPress Line Scan Cameras in 6 Gbit/s Mode with Link Aggregation 4 on the ironman Frame Grabber
- 211. Basic Acquisition for Grayscale CoaxPress Line Scan Cameras in 6 Gbit/s Mode with Link Aggregation 4 on the ironman Frame Grabber
- 212. Sinewave
- 213. FFT Result
- 214. FFT Result
- 215. Basic design structure
- 216. Content of box JPEGBlockSorter8x8
- 217. Rearangement of Pixel in JPEGBlockSorter8x8
- 218. Content of SplitImage box
- 219. Content of the RemoveFillByte box
- 220. Content of the RestartMarker box
- 221. Basic design structure
- 222. Top level design structure
- 223. Basic implementation of grayscale JPEG compression using operator JPEG_Encoder
- 224. Top level design structure
- 225. Basic implementation of color JPEG compression using user library elements
- 226. Artificial test image
- 227. Straight edge
- 228. Diagonal edge
- 229. Curved edge
- 230. Periodic structure
- 231. Bayer pattern
- 232. Basic design structure
- 233. Content of NearestNeighbour
- 234. Basic design structure
- 235. Content of HierarchicalBox Laplace
- 236. Content of HierarchicalBox SortToComponents
- 237. Basic design structure
- 238. Interpolation step 1 of the Bayer-demosaicing process
- 239. Content of ColourInterpolation
- 240. Content of the HierarchicalBox BlueAndRed
- 241. Original color image
- 242. Image demosaiced with the algorithm of Laroche et al. [Lar94]
- 243. Image demosaiced with an bilinear
algorithm - 244. Content of ColourInterpolation for the modified Laroche filter.
- 245. Sensor layout of a bilinear line scan camera with color pattern Red/BlueFollowedByGreen_GreenFollowedByBlue/Red
- 246. Basic design structure of "BilinearBayer_RG_GB.va"
- 247. Content of HierarchicalBox DeBayer
- 248. Content of HierarchicalBox DeBayerEnhancedRAW
- 249. Kernel components created in HierarchicalBox MakeKernel
- 250. Content of HierarchicalBox DeBayerRAW
- 251. Sensor layout of a bilinear line scan camera with color pattern Red/BlueFollowedByBlue/Red_GreenFollowedByGreen
- 252. Basic design structure of "BilinearBayer_RB_GG.va"
- 253. Content of HierarchicalBox DeBayer
- 254. Content of HierarchicalBox DeBayerEnhanced
- 255. Kernel components selected in HierarchicalBox DeBayerEnhanced by operator SelectSubKernel3x2
- 256. Content of HierarchicalBox DeBayerFast
- 257. Pre-Sorting of Color Components
- 258. Simulation Result of Pre-Sorted Color Components
- 259. Parameter Setting for XOffset of the ImageBufferMultiRoI Operator
- 260. Pre-Sorting for Color Separation by collecting eight successive pixel of the same component.
- 261. Color Separation with FrameBufferRandomRead
- 262. Address Generator for FrameBufferRandomRead Input
- 263. Block Diagram of the applet Hardware Test
- 264. Hardware Test Process0
- 265. Hardware Test Process1
- 266. Applet Hardware Test use of Parameter Translates and References in microDisplay
- 267. Applet Hardware Test Implementation for RAM Test, DMA Perfomance Test and Camera Acquisition
- 268. Use of FloatParamTranslator to Convert from Frames per Second to Ticks
- 269. Use of IntParamTranslator for easy Setting of the Width and Height in the Applet
- 270. Basic design structure of the VA design "TriggerAndImageStatistics.va"
- 271. Content of HierarchicalBox TriggerAnalysis
- 272. Content of HierarchicalBox CameraLink_InputStatistics
- 273. Content of HierarchicalBox Trigger_Statistics
- 274. Content of HierarchicalBox DelayAnalysis
- 275. Content of HierarchicalBox ImageAnalysis
- 276. Basic design structure of the VA design "GeometricTransformation_FrameBufferRandomRead.va"
- 277. Content of HierarchicalBox"GeometricTransformation"
- 278. Content of HierarchicalBox CoordinateTransformation
- 279. Content of HierarchicalBox OutputImage
- 280. Content of HierarchicalBox InverseTransformation
- 281. Source image [Ope16a]
- 282. Rotated and translated target image
- 283. Basic design structure of the VA design "GeometricTransformation_ImageMoments.va"
- 284. Content of the HierarchicalBox GeometricTransformation
- 285. Content of HierarchicalBox CoordinateTransformation
- 286. Content of HierarchicalBox InverseTransformation
- 287. Content of HierarchicalBox GeometricTransformation
- 288. Source image (dimension: 640x240 pixels)
- 289. Position and orientation corrected target image (dimension: 256x128 pixels)
- 290. Example: 8 Pixels are stored in one DRAM cell
- 291. Content of HierarchicalBox FrameBufferRandomRead_Par8
- 292. Basic design structure of the VA design "GeometricTransformation_DistortionCorrection.va"
- 293. Content of HierarchicalBox CoordinateTransformation
- 294. Content of HierarchicalBox KeystoneCorrection
- 295. Content of HierarchicalBox DistortionCorrection
- 296. Content of HierarchicalBox DistortionCoefficient
- 297. Example Source Image [Ope16a]
- 298. Distortion and Keystone corrected target image
- 299. Rotated, distortion and Keystone corrected target image
- 300. Basic design structure of the VA design "DistortionCorrection.va"
- 301. Content of HierarchicalBox DistortionCorrection
- 302. Content of HierarchicalBox InverseCorrection
- 303. Basic design structure
- 304. Content of ImageMoments
- 305. Content of the HierarchicalBox orientation_theta
- 306. Content of the HierarchicalBox eccentricity
- 307. Skew of a scanned object resulting from camera misalignment
- 308. Basic design structure
- 309. Content of HierarchicalBox LineShear
- 310. Content of HierarchicalBox ExtractInteger
- 311. Content of HierarchicalBox Select
- 312. Content of HierarchicalBox TransformedYCoordinate
- 313. Shift corrected image
- 314. Basic design structure for scaling a line camera image
- 315. Components of Transformation
- 316. Components of WordToRead
- 317. Components of PixelPicker
- 318. Content of Pick_0
- 319. Components of Interpolation
- 320. Basic design structure for "TapSorting_2XE_1Y.va"
- 321. Basic design structure of "TapSorting_2X_2Y.va"
- 322. Content of the HierarchicalBox Address in "TapSorting_2X_2Y.va"
- 323. Basic design structure of "TapSorting_8X_1Y.va"
- 324. Content of the HierarchicalBox Sorting_8X_1Y
- 325. Content of the HierarchicalBox Address in "TapSorting_8X_1Y.va"
- 326. Basic design structure
- 327. Content of box Trigger
- 328. Content of box HDR
- 329. Content of component Red in Image1
- 330. Content of box Red under HDR
- 331. Content of box LDR in the designs "HDR_CRC_Bayer.va" and "HDR_CRC_Color.va"
- 332. Content of box LDR in the design "HDR_CRC_Gray.va"
- 333. Basic design structure
- 334. Content of box HDR
- 335. Content of Red in box Image1
- 336. Content of Red in box HDR
- 337. Basic design structure of "ExposureFusion.va"
- 338. Content of HierarchicalBox ExposureFusion
- 339. Content of HierarchicalBox ImageComposition
- 340. Content of HierarchicalBox Weight
- 341. Content of HierarchicalBox Red in box Weight
- 342. Content of HierarchicalBox Red in box ImageComposition
- 343. Example input images with different exposure times
- 344. Result image of the 5 example input images after exposure fusion
- 345. Basic design structure
- 346. Content of HierarchicalBox DepthFromFocus
- 347. Content of HierarchicalBox CompareContrast
- 348. Content of HierarchicalBox SelectDepthIndex
- 349. Content of HierarchicalBox SelectPixelValue
- 350. Content of HierarchicalBox LastImageOfSequenceOnly
- 351. Basic Design structure of the VA designs "HOG_9Bins_Histogram.va","HOG_9Bins_HistogramMax.va" and "HOG_4Bins_HistogramMax.va"
- 352. Content of HierarchicalBiox HOG
- 353. Content of HierarchicalBox GradientFilter
- 354. Content of HierarchicalBox MagnitudeOrientation
- 355. Content of HierarchicalBox Histogram
- 356. Content of HierarchicalBox Bin1
- 357. Content of HierarchicalBox ConcatenateWithNeighbors
- 358. Content of HierarchicalBox GetHistogramMax
- 359. Basic design structure of the VA design "PrintInspection_Blob.va"
- 360. Content of the HierarchicalBox FindPatterns
- 361. Content of the HierarchicalBox ExtractCandidates
- 362. Content of the HierarchicalBox DetermingCOGTemplates
- 363. Content of the HierarchicalBox TemplateMatching
- 364. Content of the HierarchicalBox COG_Angle
- 365. Basic design structure of the VA design "PrintInspection_ImageMoments.va"
- 366. Basic design structure of "NormalizedCrossCorrelation.va"
- 367. Test image "PCB.tif"
- 368. Content of HierarchicalBox NCC
- 369. Content of HierarchicalBox Division
- 370. result image with "1" at object positions (zoomed view)
- 371. Hierarchical Box ImageTrigger of the TrgPortLine Rebuild Example
- 372. Hierarchical Box LineTrigger of the TrgPortLine Rebuild Example
- 373. Graphical programming of image processing applications on FPGAs
- 374. Objects Visualized by Colored Boxes
- 375. 4-Connected Neighborhood
- 376. 8-Connected Neighborhood
- 377. Pixels allocated to objects in a 4-connected neighborhood (left) and an 8-connected neighborhood (right). All colored pixels represent foreground pixels where their allocation to objects is visualized by differing colors.
- 378. 4-connected neighborhood: Contour Orthogonal = 30, Diagonal = 0
- 379. 8-connected neighborhood: Contour Orthogonal = 14, Diagonal = 8
- 380. Calculation of the perimeter using an 8-connected neighborhood (left) and a 4-connected neighborhood (right)
- 381. Blob Analysis Operators
- 382. Behavior of the Blob Analysis 1D Operator
- 383. Synchronization of the Blob 1D Operator in a VisualApplets Network
- 384. Blob 1D Timing - Generation of New Frames
- 385. Blob 1D Timing - Suppression of Empty Frames
- 386. Blob 1D Timing - Constant Flush
- 387. Blob 1D Timing - Discarding of Objects
- 388. Simulation Scenario 1 - Flush and Y0 Relation
- 389. Simulation Scenario 2 - Flush Pixel Position
- 390. Simulation Scenario 3 - Discarded Flush Pixel at End of Frame
- 391. Simulation Scenario 4 - Multiple Blobs
- 392. Formula for calculating the minimum input image width
- 393. RAM architecture
List of Tables
- 1. Operator Types
- 2. List of Device Resources
- 3. Commands for Creating and Editing a VA Design in Tcl
- 4. Command Line Options and According Arguments
- 5. Shortcut List for Main Program Window
- 6. Shortcut List for Simulation Viewer
- 7. List of Basic Acquisition Examples
- 8. Design Versions for Grayscale JPEG Encoding
- 9. Design Versions for Color JPEG Encoding
- 10. List of Bayer Demosaicing Examples
- 11. Overview of Color Separation Examples
- 12. List of Geometric Transformation Examples
- 13. Reading Cycles
- 14. Files and their corresponding lookup tables in Visual Applets
- 15. Examples of tap geometries
- 16. Available Libraries
- 17. Operators of Library Accumulator
- 18. Operators of Library Arithmetics
- 19. Operators of Library Base
- 20. Examples
- 21. Examples
- 22. Examples
- 23. Operators of Library Blob
- 24. Explanation of Blob Error Flags
- 25. Explanation of Blob Error Flags
- 26. Operators of Library Color
- 27. Operators of Library Compression
- 28. Operators of Library Debugging
- 29. Operators of Library Filter
- 30. Operators of Library Logic
- 31. Memory Types of Operators in the Library Memory
- 32. Individual Latencies of the Operators in Library Memory
- 33. Operators of Library Memory
- 34. Data types supported by reference operators
- 35. Operators of Library Parameters
- 36. Basic operations
- 37. Functions
- 38. Basic operations
- 39. Functions
- 40. Operators of Library Hardware Platform
- 41. Mapping VA notation and CL Specification Version 2.1
- 42. Mapping VA notation and CL Specification Version 2.1
- 43. Mapping VA notation and CL Specification Version 2.1
- 44.
- 45.
- 46.
- 47.
- 48. Operators of Library Prototype
- 49. Operators of Library Signal
- 50. Operators of Library Synchronization
- 51. Operators of Library Transformation
- 52. Hardware Configuration microEnable IV and PixelPlant
- 53. Hardware Configuration microEnable 5 ironman
- 54. Hardware Configuration LightBridge and microEnable 5 marathon
- 55. List of Device Resources microEnable IV and PixelPlant
- 56. List of Device Resources microEnable 5 ironman
- 57. List of Device Resources LightBridge and microEnable 5 marathon
List of Equations
