In designs utilizing PixelToSignal modules during simulation, in some cases an early abort of processing could occur when the simulation of data flow synchronization was activated (default). This has been fixed. (9622)
In designs utilizing PixelToImage modules during simulation, in some cases an early abort of processing could occur when the simulation of data flow synchronization was activated (default). This has been fixed. (9622)
PixelToImage now uses a simple simulation model emitting a zero pixel for each incoming pixel at port Sample.
The JPEG_Encoder operator can now be used also with non-stoppable sources. In this context, a new parameter InfiniteSource and an overflow management has been implemented. To use the operator with non-stoppable sources, you need to set parameter InfiniteSource to Enabled.
The CameraLink interface on VCL/VCLx platforms was missing clock management placement constraints. In most designs, Vivado placed the related clock managers still in correct positions due to the correspondent IO pin locations. However, under unknown circumstances it could happen that Vivado created an illegal placement which lead to an error in the Place & Route build step. The placement of the CameraLink clock managers is now fixed and thus, this issue can never occur again. (9648)
The visibility of the current FPGA clock setting (for mE5 designs) has been improved. Furthermore, a warning message occurs when the clock frequency is set to a very high value, as increasing the clock frequency may result in a build flow fail because the timing constraints can't be met. Whether the build flow with high clock settings succeeds or not strongly depends on the content of the VisualApplets design. (8513)\
The documentation for operator RGB2HSI now names the color space conversion the operator actually carries out: The operator implements the RGB to HSL (Hue Saturation Luminance) color space conversion, and NOT RGB to HSI (Hue Saturation Intensity) or RGB to HSV (Hue Saturation Value).