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New Features in VisualApplets 3.2.0#

JPEG Compression (Compression Library Feature)#

New JPEG Compression Operator#

  • VisualApplets provides a new JPEG operator JPEG_Encoder. The operator performs a JPEG compression of grayscale 8-bit images. It is available for the following hardware platforms:

    • microEnable 5 marathon frame grabbers
    • microEnable 5 ironman frame grabbers

Library JPEG Color#

  • VisualApplets provides a new user library JPEG_Color that allows JPEG compression of color images. The library elements are tailored for the following hardware platforms: 
  • microEnable 5 marathon frame grabbers  
  • microEnable 5 ironman frame grabbers

Tcl (Expert Feature)#

Script Collection#

  • The graphical user interface of VisualApplets offers a new pane Script Collection that allows Tcl users to manage, parametrize and execute their Tcl scripts without leaving the VA GUI.

New commands for build flow#

The Tcl feature of VisualApplets incorporates four new commands for the build flow:

  • Drc: command for starting the first level of the Design Rule Check.

  • Drc2: command for starting the second level of the Design Rule Check.

  • SelectBuildConfiguration: command for selecting a saved build configuration as active build configuration.

  • Build: command for starting the build flow.

  • Tcl command GetDesignProperty has been extended so that the file path of the currently loaded design can be queried now. (8518)

  • You can select to have the maximal data throughput rate displayed for each link in the design window. You can switch the display on/off via button in the toolbar. The display may be convenient to monitor and calculate the bandwidth on links during design time. (See also section Changes and Bug Fixes/Automatic Bandwidth Analysis.)

Hierarchical Boxes#

  • You can select a number of elements and put them into a hierarchical box via mouse click, using the new option Move to Hierarchical Box. (5128)
  • You can rename the input and output ports of hierarchical boxes. Use the context menu of the module nodes for renaming. (3528)
  • You can re-arrange the order of input and output ports of a hierarchical box (via options Move Port Up/Move Port Down from the context sensitive menu). The re-arrangement of port order has no impact on the functionality of the hierarchical box. The re-arranged ports are linked to the same inner and outer design elements as before.

User Library#

  • You can equip your user library elements now with a GUI icon and with a help file for the users of your custom library element. (7776)
  • You can rename the input and output ports of user library elements. Use the context menu of the module nodes for renaming. (3528)

Library Parameters#

  • Several operators of library Parameters now support the new properties 'Description' and 'Unit'. (7857)
  • Within protected user library elements, operators of library Parameters don't require a VA Expert or Parameters Library license any more. So such modules may be distributed to customers which don't have a VA Expert or Parameters Library license. (9244)

Operators#

CLHSSingleCamera#

  • The CLHS camera operator CLHSSingleCamera has been extended and now also supports acquisition format RAW. In RAW mode, all line and frame markers coming in from the camera will be ignored. "RAW" mode is used to support complex link structures and is exclusively available in operator CLHSSingleCamera.
  • CLHS camera operator CLHSSingleCamera now allows to define a second optional output port HeaderO to allow for dynamic configuration. This new output port HeaderO provides the header information of the video package that is currently worked on. The port provides the header information in a pixel of a width of 64 bit.
  • Operator CLHSSingleCamera now supports complex link structures.

SignalToPixel#

  • Operator SignalToPixel has a variable number of input ports (up to 64 per operator instance).

ABS#

  • Operator ABS now also supports color formats. Each component in a color format is handled separately. (2687)

ModuloCount#

  • Operator ModuloCount now supports images with variable line length and with empty lines also in simulation.
  • For parameter Divisor, the 32-bit limit has been removed.

FrameMax#

  • Operator FrameMax now also supports images with variable line length and with empty lines. (2692)
  • Simulation of operator FrameMax now works correctly also in 0D and 1D format (image protocols VALT_IMAGE0D and VALT_IMAGE1D).

FrameMin#

  • Operator FrameMin now also supports images with variable line length and with empty lines. (2693)
  • Simulation of operator FrameMin now works correctly also in 0D and 1D format (image protocols VALT_IMAGE0D and VALT_IMAGE1D).

FrameSum#

  • Operator FrameSum now also supports variable line length and empty lines in a non-empty image. (2694)

RowMax#

  • Operator RowMax now also supports variable line length and empty lines in a non-empty image. (2696)
  • Simulation of operator RowMax now works correctly also in 0D and 1D format (image protocols VALT_IMAGE0D and VALT_IMAGE1D).

RowMin#

  • Operator RowMin now also supports variable line length and empty lines in a non-empty image. (2697)
  • Simulation of operator RowMin now works correctly also in 0D and 1D format (image protocols VALT_IMAGE0D and VALT_IMAGE1D).

RowSum#

  • Operator RowSum now also supports variable line length and empty lines in a non-empty image. (2698)

Histogram#

  • Operator Histogram now also supports images with variable line length and with empty lines. (3357)
  • An image is now allowed to be smaller than the maximum image width. (3357)

CameraControl#

  • In CL Base Mode, operator CameraControl, Port B: The polarity of ports CC2 and CC4 has been inverted. Now the polarity behaves the same way as on Port A. (9167)

MergeParallel#

  • The operator MergeParallel got a new parameter MergeMode which defines how parallel input pixels are arranged in the output link. (5862)

New Simulation Engine#

  • VisualApplets is equipped with a new simulation Engine. The new engine gives a very realistic depiction of the data flow and allows simulating blocked image data streams. Optionally, the new simulation engine can be disabled in cases where the old simulation engine is preferred. (Enable/disable in Menu System Settings->Simulation->Simulate data flow synchronization.)

Netlist Style Selectable via GUI#

  • You can select the style for netlist generation now directly from the GUI. Under menu Settings -> System Settings -> Global Build Special Settings -> Style of synthesized design netlists you can change the netlist style from Default to Optimized. Use Optimized when building timing-critical designs to try to achieve a better timing closure in the build flow. VisualApplets will generate the FPGA netlist with an alternative naming scheme which in some cases helps the Xilinx tool flow to generate a better distribution of logic on the FPGA. (See also Release Notes VisualApplets 3.1.1, Build/New Option for Meeting Timing Constraint.) In earlier versions (since VisualApplets 3.1.1), the mode Optimized was already available via environment variable VA_NETLIST_STYLE.

Ultrascale/Ultrascale+ FPGAs Supported#

  • Embedded VisualApplets (eVA) now supports platforms working with Ultrascale or Ultrascale+ FPGAs. (8458)
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