Operator MULT multiplies the values at input link I1 by the values at input link I2. At output link O, the result of the multiplication is provided.
Operator MULT supports asymmetric arithmetic types on its inputs, i.e., SIGNED and UNSIGNED may be mixed up so that you can multiply an unsigned multiplier with a signed multiplicand or a signed multiplier with an unsigned multiplicand as well as a signed multiplier with a signed multiplicand or an unsigned multiplier with an unsigned multiplicand.
A multiplication requires many FPGA resources. For scaling with a constant use operator SCALE or ShiftLeft instead. Moreover, most frame grabbers include embedded arithmetic logic units (embedded multipliers). Use operator HWMULT to save resources.
|Input Links||I1, multiplicand 1
I2, multiplicand 2
|Output Link||O, multiplication result|
The use of operator MULT is shown in the following examples:
Example - Histogram thresholding