Area of Interest (AOI)

See Region of Interest.

Block RAM

See FPGA Internal Block RAM.


A Basler hardware. Usually, a board is represented by a frame grabber. Boards might comprise multiple devices.

Board ID Number

An identification number of a board in a PC system. The number is not fixed to a specific hardware but has to be unique in a PC system.

Camera Index

The index of a camera connected to a frame grabber. The first camera will have index zero. Mind the difference between the camera index and the frame grabber camera port.

See also Camera Port.

Camera Port

The frame grabber connectors for cameras are called camera ports. They are numbered {0, 1, 2, ...} or enumerated {A, B, C, ... }. Depending on the interface one camera could be connected to multiple camera ports. Also, multiple cameras could be connected to one camera port.

Camera Tap

See Tap.


A board can consist of multiple devices. Devices are numbered. The first device usually has number one.

Direct Memory Access (DMA)

A DMA transfer allows hardware subsystems within the computer to access the system memory independently of the central processing unit (CPU).

DMA is used for data transfer such as image data between a board e.g. a frame grabber and a memory of the host system. Data transfers can be established in multiple directions i.e. from a frame grabber to the PC (download) and from the PC to a frame grabber (upload). Multiple DMA channels may exist for one board. Control and configuration data usually do not use DMA channels.

Distributed RAM

See FPGA Distributed RAM.

DMA Channel

See DMA Index.

DMA Index

The index of a DMA transfer channel.

See also Direct Memory Access.

FPGA Distributed RAM

Logic cells of the FPGA which are used as memory. Also called LUT RAM

FPGA Internal Block RAM

Memory blocks in the FPGA. Each FPGA includes a limited number of Block RAMs.

Frame Grabber RAM

A memory on the frame grabber but not in the FPGA. Usually DRAM.

Hardware Applet (HAP)

A hardware applet file is a build VisualApplets project. It can be loaded to licensed hardware devices e.g. frame grabbers. A HAP includes the FPGA bitstream as well as the software interface to access data and parameter. A HAP can only be used on one target runtime defined before the build was executed.

Host PC

The computer the frame grabber or device is attached to.

Least Significant Bit (LSB)

The bit position in a binary value having the lowest value i.e. the right-most bit.


See Operator Library.


See FPGA Distributed RAM.

Mebibyte (MiB)

One Mebibyte (MiB) are 1.048.576 Byte.

Megabyte (MB)

One Megabyte (MByte or MB) are 1,000,000 Byte.


An instantiated operator in a VisualApplets diagram. See Operator.

Most Significant Bit (MSB)

The bit position in a binary value having the greatest value i.e. the left-most bit.


Represents an image-, data-, or signal-processing functionality. Is organized in operator libraries.

Operator Library

Operator Libraries include operators. Operators from an operator library can be used in a VisualApplets diagram.


Memory on the PC. Usually system memory or main memory on the mainboard. Accessed from the frame grabber via Direct Memory Access .


See Camera Port.


An image or signal data processing block. A process can include one or more cameras, one or more DMA channels and modules.

Random Access Memory (RAM)

A memory which can be directly accessed for reading and writing in any random order.

Region of Interest (ROI)

A part a frame. Mostly rectengular and within the original image boundaries. Defined by coordinates. The frame grabber cuts the region of interest from the camera image. A region of interest might reduce or increase the required bandwidth.

Sensor Tap

See Tap.


Some cameras have multiple taps. This means, they can acquire or transfer more than one pixel at a time which increses the camera's acquisition speed. The camera sensor tap readout order varies. Some cameras read the pixels interlaced using multiple taps, while some cameras read the pixel simulatiously from different locations on the sensor. The reconstruction of the frame is called sensor readout correction.

The Camera Link interface is also using multiple taps for image tranfer to increase the bandwidth. These taps are independent from the sensor taps.


In machine vision and image processing, a trigger is an event which causes an action. This can be for example the initiation of a new line or frame acquisition, the control of external hardware such as flash lights or actions by a software applications. Trigger events can be initiated by external sources, an internal frequency generator (timer) or software applications.

Trigger Input

A logic input of a trigger IO. The first input has index 0. Check mapping of input pins to logic inputs in the hardware documentation.

Trigger Output

A logic output of a triger IO. The first output has index 1. Check mapping of output pins to logic outputs in the harware documentation.