Now you have finished the example design Sobel_Filter.va and
want to translate the design into a hardware applet. For this translation process,
called build you need to select the correct Xilinx build
settings. Open Settings+Build Settings, and select the batch file settings64.bat of your
corresponding Xilinx version (recommended: Xilinx Vivado 2018.2) from your file
system and confirm with OK. You find a detailed description of editing the build
settings under 'Build Settings'.
VisualApplets now uses the Xilinx tools to translate the application into the FPGA
bitstream, i.e., the program or applet.
The duration of this process depends on the complexity of the design. The build of
highly complex designs might take several hours. For this example implementation
Sobel_Filter.va, the build time is about 15 minutes. After
successful build, the applet is fully generated. The name of the applet
(*.hap file) is the same as the name of the design file
(*.va): Sobel_Filter.hap
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